450NX Datasheet, PDF (45/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3
BINIT# on System Bus Time-outs.
If this bit is set, and the BINIT# Driver Enable is set, the MIOC will assert BINIT# on a
system bus access time-out. Default=0.
2
AERR# Driver Enable.
If set, parity errors on the system bus address and request signals are reported by
asserting AERR#. Default=0.
1
BERR# Driver Enable.
If set, BERR# will be asserted for uncorrectable ECC errors on memory reads or data
arriving from the system data bus. Default=0.
0
BINIT# Driver Enable.
If set, BINIT# will be asserted upon detecting protocol violations on the system bus.
This enable should only be cleared for system boot. In normal operation, this enable
must be set. Default=0.
3.3.14 ERRSTS: Error Status Register
Address Offset: 44-45h
Default Value: 0000h
Size:
16 bits
Attribute: Read/Write Clear, Sticky
This register records error conditions detected in the address or controls of the system bus, or
in the MIOC itself. Recording of these error conditions is controlled via the ERRCMD register.
ERRSTS is sticky through reset, and bits will remain set until explicitly cleared by software
writing a 1 to the bit.
Bits Description
15:13 reserved (0)
12
Received Hard Fail Response on System Bus.
This flag is set when the MIOC detects a Hard Fail response on the system bus. If the
BINIT# Driver Enable in the ERRCMD register is set, BINIT# is also asserted.
11
Expander Bus #1 Protocol Violation Flag.
This flag is set when the Expander Bus #1 interface receives unexpected data that the
MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD
register, BINIT# is also asserted.
10
Expander Bus #0 Protocol Violation Flag.
This flag is set when the Expander Bus #0 interface receives unexpected data that the
MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD
register, BINIT# is also asserted.
9
Performance Monitor #1 Event Flag.
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. While this bit is set, the INTREQ# line will be asserted.
8
Performance Monitor #0 Event Flag.
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. While this bit is set, the INTREQ# line will be asserted.
Intel® 450NX PCIset
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