450NX Datasheet, PDF (104/248 Pages) Intel Corporation – Intel 450NX PCIset

7. Transaction Summary
Distributed DMA
Distributed DMA across the PCI bus is not supported by the Intel 450NX PCIset. This
function is incompatible with the passive release mechanism portion of the PHOLD#/PHLDA#
protocol used to grant PCI bus access to south bridges.
Accesses Prohibited to Third-Party Agent
The Intel 450NX PCIset only supports inbound south bridge accesses to memory. Inbound
accesses from a south bridge using the PHOLD#/PHLDA# protocol, directed to a third-party
agent on the system bus, are not supported. Such accesses, involving interactions with
unknown and unpredictable agents, could violate the rules governing the PHOLD#/PHLDA#
protocol, potentially leading to deadlocks.
7.4
Configuration Accesses
The PCI specification defines two mechanisms to access configuration space, Mechanism #1
and Mechanism #2. The Intel^® 450NX PCIset supports only Mechanism #1.
Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at
location 0CF8h, and a data register (CONFIG_DATA) at location 0CFCh. The Intel 450NX
PCIset provides a PCI-compatible configuration space for the MIOC, and one for each PCI bus
in the PXB.
• If the MIOC detects the I/O request is a configuration access to its own configuration
space, it will service that request entirely within the MIOC. Reads result in data being
returned to the system bus.
• If the MIOC detects the I/O request is a configuration access to a PXB configuration space,
it will forward the request to the appropriate PXB for servicing. The request is not
forwarded to a PCI bus. Reads will result in data being returned by the PXB through the
MIOC to the system bus.
• If the MIOC detects the I/O request is a configuration access to a third-party agent on the
system bus, it will leave the access unclaimed on the system bus. The third-party agent
may claim the access, with reads resulting in data being returned by the third-party agent
to the system bus.
• Otherwise, the access is forwarded on to the PXB to be placed on the PCI bus as a
Configuration Read or Configuration Write cycle. Reads will result in data being
returned through the PXB and MIOC back to the system bus, just as in normal Outbound
Read operations.
7-6
Intel® 450NX PCIset