450NX Datasheet, PDF (27/248 Pages) Intel Corporation – Intel 450NX PCIset

2.6 Expander Interface
2.5.2.2
DRAM / MUX Interface
Q0D[35:0]
Memory Data, Interleave 0
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave zero.
Q1D[35:0]
Memory Data, Interleave 1
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave one.
Q2D[35:0]
Memory Data, Interleave 2
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave two.
Q3D[35:0]
Memory Data, Interleave 3
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave three.
2.5.2.3
RCG / MUX Interface
AVWP#
Advance MUX Write Path Pointers
AGTL+ RCG→ MUX
This signal is activated by an RCG after performing a memory write.
LDSTB#
Load Data Strobe
AGTL+ RCG→ MUX
This signal controls when read data is latched from the DRAM data bus.
LRD#
Load Read Data
AGTL+ RCG→ MUX
This signal indicates when read data is ready to load from the DRAMs.
WDME#
Write Data to Memory Enable
AGTL+ RCG→ MUX
This signal enables the MUXes to drive write data to the DRAMs.
2.6
Expander Interface
The MIOC component has two Expander interfaces, one for each of the two PXBs supported
by Intel^® 450NX PCIset. These two high speed, low latency interfaces are identified as the X0
bus and the X1 bus groups.
Each signal name includes a “p”, indicating the Expander port. On the MIOC, p = 0 or 1,
designating one of the two interfaces. On the PXB, p is not used.
XpADS#
Address / Data Strobe.
AGTL+ MIOC↔ PXB
Bidirectional signal asserted by the sending agent during data transmission.
XpBE[1:0]#
Byte Enables.
AGTL+ MIOC↔ PXB
Bidirectional signals indicating valid bytes during the data phases of a
transmission.
Intel® 450NX PCIset
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