450NX Datasheet, PDF (6/248 Pages) Intel Corporation – Intel 450NX PCIset

CONTENTS
6.1.4 Card to Card (C2C) Interleaving .................................................................................................... 6-5
6.1.5 Memory Initialization ...................................................................................................................... 6-6
Chapter 7
Transaction Summary ......................................................................................................................... 7-1
7.1 Host To/From Memory Transactions ........................................................................................................... 7-1
7.1.1 Reads and Writes .......................................................................................................................... 7-1
7.1.2 Cache Coherency Cycles .............................................................................................................. 7-1
7.1.3 Interrupt Acknowledge Cycles ....................................................................................................... 7-1
7.1.4 Locked Cycles ............................................................................................................................... 7-1
7.1.5 Branch Trace Cycles ..................................................................................................................... 7-2
7.1.6 Special Cycles ............................................................................................................................... 7-2
7.1.7 System Management Mode Accesses .......................................................................................... 7-3
7.1.8 Third-Party Intervention ................................................................................................................. 7-3
7.2 Outbound Transactions ................................................................................................................................ 7-4
7.2.1 Supported Outbound Accesses ..................................................................................................... 7-4
7.2.2 Outbound Locked Transactions ..................................................................................................... 7-4
7.2.3 Outbound Write Combining ........................................................................................................... 7-4
7.2.4 Third-Party Intervention on Outbounds ......................................................................................... 7-4
7.3 Inbound Transactions .................................................................................................................................. 7-5
7.3.1 Inbound LOCKs ............................................................................................................................. 7-5
7.3.2 South Bridge Accesses ................................................................................................................. 7-5
7.4 Configuration Accesses ............................................................................................................................... 7-6
Chapter 8
Arbitration, Buffers & Concurrency ................................................................................................... 8-1
8.1 PCI Arbitration Scheme ............................................................................................................................... 8-1
8.2 Host Arbitration Scheme .............................................................................................................................. 8-1
8.2.1 Third Party Arbitration .................................................................................................................... 8-2
8.3 South Bridge Support ................................................................................................................................... 8-2
8.3.1 I/O Bridge Configuration Example. ................................................................................................ 8-2
8.3.2 PHOLD#/PHLDA# Protocol ........................................................................................................... 8-3
8.3.3 WSC# Protocol .............................................................................................................................. 8-3
Chapter 9
Data Integrity & Error Handling .......................................................................................................... 9-1
9.1 DRAM Integrity ............................................................................................................................................. 9-1
9.1.1 ECC Generation ............................................................................................................................ 9-1
9.1.2 ECC Checking and Correction ...................................................................................................... 9-1
9.1.3 ECC Error Reporting ..................................................................................................................... 9-1
9.1.4 Memory Scrubbing ........................................................................................................................ 9-2
9.1.5 Debug/Diagnostic Support ............................................................................................................. 9-2
9.2 System Bus Integrity .................................................................................................................................... 9-2
9.2.1 System Bus Control & Data Integrity ............................................................................................. 9-3
9.3 PCI Integrity ................................................................................................................................................. 9-3
9.4 Expander Bus .............................................................................................................................................. 9-3
Chapter 10
System Initialization .......................................................................................................................... 10-1
10.1 Post Reset Initialization .............................................................................................................................. 10-1
10.1.1 Reset Configuration Using CVDR/CVCR .................................................................................... 10-1
10.1.1.1 Configuration Protocol ................................................................................................ 10-1
10.1.1.2 Special Considerations for Third-Party Agents .......................................................... 10-2
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Intel® 450NX PCIset