450NX Datasheet, PDF (64/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3.4.3
CLS: Cache Line Size
Address Offset: 0Ch
Default Value: 08h
Bits Description
Size:
8 bits
Attribute: Read/Write
7:0 Cache Line Size
This field specifies the cache line size, in 32-bit Dword units. The Intel^® 450NX PCIset
supports only one value: 8 Dwords (32 bytes). Default=08h.
3.4.4
CONFIG: Configuration Register
Address Offset: 40-41h
Default Value: 2310h
Size:
16 bits
Attribute: Read/Write, Read-Only
Bits Description
15
reserved (0)
14
PCI Bus Lock Enable.
This mode works only if internal bus arbitration is selected. When set, the internal
arbiter detects when the lock is established and inhibits a PCI bus grant to all agents
except the agent that established the lock.
Default=0.
13
WSC# Assertion Enable.
If cleared, the WSC# signal will always remain asserted. While asserted, writes
continue to be accepted from the PIIX even with writes outstanding. This option is
provided to allow improved performance in systems with ISA masters that desire to
write to main memory.
Default=1.
12
PCI-TPA Prefetch Line Enable (PLE).
If set, inbound line accesses (e.g., MRM and MRL accesses) to third-party space are
treated as prefetchable. Default=0.
11
PCI-TPA Prefetch Word Enable (PWE).
If set, inbound sub-line accesses (e.g., MR accesses) to third-party space are treated as
prefetchable. Default=0.
10
Block Requests.
This enable is provided for debug, diagnostic and error recovery purposes. If set, the
internal arbiter ignores all further REQ[0:5]# assertions by any of the six PCI agents,
and will deassert any current PCI agent’s GNT# in order to prevent further inbound
transactions from a parking agent. This enable has no effect if the PXB is configured to use
external arbitration. Default=0.
9
I/O Address Mask Enable.
If set, on outbound I/O accesses the PXB will force A[31:16] to zero before placing the
address on the PCI bus. Default=1.
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Intel® 450NX PCIset