450NX Datasheet, PDF (145/248 Pages) Intel Corporation – Intel 450NX PCIset

12.6 I/O Signal Simulations: Ensuring I/O Timings
HCLKIN
V
Tx
MAX
Tx = Valid Delay
Figure 12-11: Valid Delay Timing
Valid
Tx
MIN
12.6 I/O Signal Simulations: Ensuring I/O Timings
It is highly recommended that system designers run extensive simulations on their Pentium^®
II Xeon™ processor/Intel^® 450NX PCIset-based designs. These simulations should include
the memory subsystem design as well. Please refer to the Pentium^® Pro Family Developer’s
Manual for more information.
12.7 Signal Quality Specifications
Signals driven by any component on the Pentium^® II Xeon™ processor bus must meet signal
quality specifications to guarantee that the components read data properly, and to ensure that
incoming signals do not affect the long term reliability of the components. There are three
signal quality parameters defined: Overshoot/Undershoot, Ringback, and Settling Limit,
which are discussed in the next sections.
12.7.1 Intel^® 450NX PCIset Ringback Specification
This section discusses the ringback specification for the parameters in the AGTL+ signal
groups on the Intel^® 450NX PCIset.
Case A requires less time than Case B from the V_REF crossing until the ringback into the
“overdrive” region. The longer time from V_REF crossing until the ringback into the
“overdrive” region required in Case B allows the ringback to be closer to V_REF for a defined
period.
Intel® 450NX PCIset
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