450NX Datasheet, PDF (58/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
Bits Description
7:0 Revision Identification Number.
This is an 8-bit value that indicates the revision identification number for the MIOC
3.3.38 ROUTE[1:0]: Route Field Seed
Address Offset: C3h, CBh
Default Value: 40h
Size:
8 bits
Attribute: Read/Write
Bits Description
7:4 Outbound-to-B Route Seed.
This field represents the “seed” value used to create the routing field for outbound
packets to the PXB’s B-port.
Default: 0100b
3:0 Outbound-to-A Route Seed.
This field represents the “seed” value used to create the routing field for outbound
packets to the PXB’s A-port.
Default: 0000b
3.3.39 SMRAM: SMM RAM Control Register
Address Offset: 6C-6Fh
Default Value: 00000Ah
Bits Description
Size:
32 bits
Attribute: Read/Write
31
SMRAM Enable (SMRAME).
If set, the SMRAM functions are enabled. Host-initiated accesses to the SMM space
can be selectively directed to memory or PCI, as defined below and in Table 3-3. If
SMRAME is cleared, SMRAM functions are disabled. Default=0.
30:27 reserved (0)
26
SMM Space Open (D_OPEN).
If set, all accesses (code fetches or data references) to SMM space are passed to
memory, regardless of whether the SMMEM# signal is asserted. D_OPEN may be set
or cleared by software. D_OPEN will also be automatically cleared, and will become
read-only, when the D_LCK enable is set. Default=0.
25
SMM Space Closed (D_CODE).
This bit should not be set unless D_OPEN=0. If D_CODE is set, only code fetches to
SMM space may be passed to the DRAM, depending on the SMMEM# signal. Data
accesses to SMM space will not be passed to the DRAM, regardless of the SMMEM#
signal. Default=0.
3-26
Intel® 450NX PCIset