450NX Datasheet, PDF (59/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
24
SMM Space Locked (D_LCK).
When software writes a 1 to this bit, the hardware will clear the D_OPEN bit, and
both D_LCK and D_OPEN then become read only. No application software, except
the SMI handler, should violate or change the contents of SMM memory. Default=0.
23:20
SMM Space Size.
This field specifies the size of the SMM RAM space, in 64 KB increments.
0h 64 KB
1h 128 KB
2h 192 KB
3h 256 KB
4h 320 KB
5h 384 KB
6h 448 KB
7h 512 KB
8h 576 KB
9h 640 KB
Ah 704 KB
Bh 768 KB
Ch 832 KB
Dh 896 KB
Eh 960 KB
Fh 1 MB
Default: 0h (64 KB).
19:16 reserved (0)
15:0 SMM Space Base Address.
This field specifies the A[31:16] portion of the SMM RAM space base address
(A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary
and the Top of Memory (TOM); however, the base address must be aligned on the
next highest power-of-2 natural boundary given the chosen size. Incorrect alignment
results in indeterminate operation. Default: 000Ah.
Table 3-3: SMRAM Space Cycles
Code
Fetch
Data
Reference
Usage
0 X X X X Normal¹
1 0 0 X 0 PCI 0a
1 0 0 X 1 DRAM
1 0 1 X 0 PCI 0A
1 0 1 X 1 DRAM
X1 1XX
1 1 0 0 X DRAM
1. SMRAM functions are disabled.
Normal¹ SMM RAM space is not supported.
PCI 0A
DRAM
Normal SMM usage. Accesses to the SMM
RAM space from processors in SMM will
access the DRAM. Accesses by processors
not in SMM will be diverted to the
compatibility PCI bus.
PCI 0A
PCI 0A
A modification of the normal SMM usage, in
which only code fetches are accepted from
processors in SMM mode.
Illegal Combination
DRAM
Full access by any agent to SMM RAM
space.
3.3.40 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB
Address Offset: D1h, D4h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
See the description of BUSNO.
Intel® 450NX PCIset
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