450NX Datasheet, PDF (85/248 Pages) Intel Corporation – Intel 450NX PCIset

4.2 I/O Space
direct the access to DRAM. Otherwise, the access will be forwarded to the compatibility PCI
bus. If SMM is not enabled in the Intel 450NX PCIset, accesses are treated normally.
4.2
I/O Space
The Intel^® 450NX PCIset allows I/O accesses to be mapped to resources supported on any of
the four PCI buses. The 64KB I/O address range is partitioned into sixteen 4 KB segments
which may be partitioned amongst the four PCI buses, as shown in Figure 4-3. Host-initiated
accesses that fall within a bus’ I/O range are directed to that bus. Segment 0 always defaults to
the compatibility PCI bus.
The Intel 450NX PCIset’s I/O Range Register defines the mapping of I/O segments to each
PCI bus. This is illustrated in Figure 4-3. Accesses that fall within an I/O address range and
forwarded to the selected PCI bus, but not claimed by a device on that bus, will time-out and
be terminated by the Intel 450NX PCIset.
I/O Space Mapping to PCI Buses
FFFF
Segment
15
F000
I/O
Space
Bus 1B
FFFF
4000
Segment
3
3000
Segment
2
2000
Segment
1000
1
Segment
0000
0
I/O
Space
Bus 1A
I/O
Space
Bus 0B
IOR.BUS1A
(top)
IOR.BUS0B
(top)
I/O
Space
Bus 0A
IOR.BUS0A
(top)
0000
Segment Configuration
ISA Alias Mode
Disabled
ISA Alias Mode
Enabled
xFFF
xFFF
xD00
xC00
xD00
xC00
x900
x800
x900
x800
x500
x400
x500
x400
x100
x000
x100
x000
Segment 0
03FF
0100
0000
Figure 4-3: I/O Space Address Mapping
The Intel 450NX PCIset optionally supports ISA expansion aliasing, as shown in Figure 4-3.
When ISA expansion aliasing is supported, the ranges designated as I/O Expansion are
internally aliased to the 0100h-03FFh range in Segment 0 before the normal I/O address
range checking is performed. This aliasing is only for purposes of routing to the correct PCI
bus. The address that appears on the PCI bus is unaltered. ISA expansion aliasing is enabled
or disabled through the ISA Aliasing Enable bit in the MIOC’s CONFIG register.
Intel® 450NX PCIset
4-5