450NX Datasheet, PDF (47/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
4
Low Expansion Gap Enable.
When set, the Low Expansion Gap (LXG) is enabled. Default=0.
3
High BIOS Space Enable.
If set, a 2 MByte space is opened at location (4 GB - 2 MB), and accesses into this
address range will be directed to the compatibility PCI bus instead of memory.
Default=1.
2
High Graphics Adapter Space Enable.
If set, a 64 KB space is opened in the upper half of the Graphics Adapter portion of the
Low Compatibility Region (address range B_0000h-BFFFFh), and accesses into this
address range will be directed to the compatibility PCI bus instead of memory.
Default=1.
1
Low Graphics Adapter Space Enable.
If set, a 64 KB space is opened in the lower half of the Graphics Adapter portion of the
Low Compatibility Region (address range A_0000h-AFFFFh), and accesses into this
address will be directed to the compatibility PCI bus instead of memory. Default=1.
0
reserved (0)
3.3.16 HDR: Header Type Register
Address Offset: 0Eh
Default Value: 00h
Size:
8 bits
Attribute: Read Only
This register identifies the header layout of the configuration space. Writes to this register
have no effect.
Bits Description
7
Multi-function Device.
The MIOC is not a multi-function device, and this bit is hardwired to 0.
6:0 Configuration Layout.
This field is hardwired to 00h, which represents the default PCI configuration layout.
3.3.17 HEL[1:0] Host Bus Error Log
Address Offset: B4-B7h
Default Value: 0000h each
Size:
16 bits each
Attribute: Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data received from
the system bus. HEL[0] logs the first error, and HEL[1] logs the second. The registers hold
their data until reloaded due to a new error condition, or until they are explicitly cleared by
software or a power-good reset.
Intel® 450NX PCIset
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