450NX Datasheet, PDF (140/248 Pages) Intel Corporation – Intel 450NX PCIset

12. Electrical Characteristics
Table 12-15: Intel^® 450NX PCIset MUX AC Specifications
Vcc₃ = 3.3 V (5%, T_CASE = 0 to 85^oC)
Symbol Parameter
Setup
Min
Memory Subsystem/
External Interface
T60
DCMPLT#
2.8
T61
DOFF[1:0]#, DSEL#,
2.8
DVALID#, WDEVT#
T60
GDCMPLT#
2.8
T67
LDSTB#
3.0
Memory Subsystem/
Internal Interface
T62
AVWP#, WDME#
3.5
T62
LRD#
3.5
T68
Q0D[35:0], Q1D[35:0],
1.0
Q2D[35:0], Q3D[35:0]
Other
T69
MRESET#
2.8
Testability Signals:
T26
TRST#
T27
TMS, TDI
5.0
T28
TDO
T29
TDO on/off delay
Hold Delay
Min Min
0.0
-0.15
0.0
0.0
-0.15
1.0
0.0
0.0
4.0
0.0
0.0
14.0
1.0
Delay
Max
2.65
2.65
3.5
10.0
25.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
6
8
6
2, 4
5
3, 7
1
1, 2
1, 2
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
Min and Max timings are measured with 0pF load.
TRST# requires a pulse width of 40 ns.
Input timings are referenced from LDSTB# rising edge. Output timings are referenced from HCLKIN.
Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous
assertion and synchronous deassertion.
Min and Max timings are measured with 0pF and 25 Ω to Vtt (1.5 V).
This input is asynchronous.
DOFF[1:0]#, DSEL#, WDEVT# max delay timing requirement from MIOC to MUX is two clock cycles.
12-16
Intel® 450NX PCIset