450NX Datasheet, PDF (48/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
Bits Description
15:8 Syndrome.
Holds the calculated syndrome that identifies the specific bit in error.
7:2 reserved (0)
1
Multiple-Bit Error Logged (MBE).
This flag is set if the logged error was a multiple-bit (uncorrectable) error.
0
Single-Bit Error Logged (SBE).
This flag is set if the logged error was a single-bit (correctable) error.
3.3.18 HXGB: High Expansion Gap Base
Address Offset: 58-5Ah
Default Value: 000000h
Bits Description
Size:
24 bits
Attribute: Read/Write
23:0 Gap Base Address.
This field specifies the A[43:20] portion of the gap’s base address, in 1 MB increments.
The A[19:0] portions of the gap’s base address are zero.
3.3.19 HXGT: High Expansion Gap Top
Address Offset: 5C-5Eh
Default Value: 000000h
Bits Description
Size:
24 bits
Attribute: Read/Write
23:0 Gap Top Address.
This field specifies the A[43:20] portion of the gap’s highest address, in 1 MB
increments. The A[19:0] portion of the gap’s top address is FFFFFh.
3.3.20 IOABASE: I/O APIC Base Address
Address Offset: 68-69h
Default Value: 0FECh
Bits Description
Size:
16 bits
Attribute: Read/Write
15:12 reserved (0)
11:0 I/O APIC Base Address.
This field specifies the A[31:20] portion of the I/O APIC Space’s base address, in 1 MB
increments. The A[43:32] and A[19:0] portions of the address are zero.
3-16
Intel® 450NX PCIset