450NX Datasheet, PDF (31/248 Pages) Intel Corporation – Intel 450NX PCIset

2.8 Component-Specific Support Signals
SMIACT#
SMI Active.
LVTTL O
This signal provides a visible indicator that the system has entered System
Management Mode.
2.8.2
PXB
INTRQ(A,B)#
Interrupt Requests
PCI OD
These pins are asserted by the PXB when an internal event occurs and sets a
status flag, and that flag has been configured to request an interrupt. There is
one pin for each side (A,B) of the PXB. The signals may be connected to the
standard PCI bus interrupt request lines.
PAMON[1:0]#
PBMON[1:0]#
Performance Monitors
LVTTL I/OD
These pins track the two performance monitoring counters associated with
each PCI bus (a,b) in the PXB. PMON[0] tracks the PMD[0] counter while
PMON[1] tracks the PMD[1] counter.
PIIXOK#
PWRGD
PIIX Reset Complete.
LVTTL I
This signal is tied to the PIIX’s CPURST output, and is used to detect when
the PIIX completes its reset functions.
Power Good
LVTTL I
This input should be driven from the MIOC's PWRGDB output.
2.8.3
RCG
BANKID#
DR50H#
DR50T#
HCLKIN
Bank Identifier
LVTTL I
This strapping pin should be tied high (deasserted), or have an external
pullup.
50ns DRAM “Here”.
LVTTL I
This strapping pin selects between 60ns and 50ns DRAM timings for this
RCG.
Deasserted: 60ns timings will be used.
Asserted: 50ns timings will be used.
50ns DRAM “There”.
LVTTL I
This strapping pin should match the DR50H# strapping pin described above.
Host Clock In
This pin receives a buffered system clock.
2.5V I
2.8.4
MUX
HCLKIN
Host Clock In
This pin receives a buffered system clock.
2.5V I
Intel® 450NX PCIset
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