450NX Datasheet, PDF (111/248 Pages) Intel Corporation – Intel 450NX PCIset

9.3 PCI Integrity
Additionally, the MIOC supports parity checking on the system address and
request/response signals.
9.2.1
System Bus Control & Data Integrity
The MIOC detects errors on the system data bus by checking the ECC provided with data and
the parity flag provided with control signals. In turn, the MIOC will generate new ECC with
data and parity with control signals so that bus errors can be detected by receiving clients.
The request control signals ADS# and REQ#[4:0] are covered with the Request Parity signal
RP#, which is computed as even parity. This ensures that it is deasserted when all covered
signals are deasserted.
The address signals A#[35:3] are covered by the Address Parity signal AP#[1:0], which is also
configured for even parity. This ensures that each is deasserted when all covered signals are
deasserted. AP#[1] covers A#[35:24] and AP#[0] covers A#[23:3].
Response signals RS#[2:0] are protected by RSP#. RSP# is computed as even parity. This
ensures that it is deasserted when all covered signals are deasserted.
9.3
PCI Integrity
The PCI bus provides a single even-parity bit (PAR) that covers the AD[31:0] and C/BE#[3:0]
lines. The agent that drives the AD[31:0] lines is responsible for driving PAR. Any undefined
signals must still be driven to a valid logic level and included in the parity calculation.
Parity generation is not optional on the PCI bus; however, parity error detection and reporting
is optional. The PXB will always detect an address parity error, even if it is not the selected
target. The PXB will detect data parity errors if it is either the master or the target of a
transaction, and will optionally report them to the system.
Address parity errors are reported using the SERR# signal. Data parity errors are reported
using the PERR# signal. The ERRCMD (Error Command) register provides the capability to
configure the PXB to propagate PERR# signaled error conditions onto the SERR# signal.
9.4
Expander Bus
Each Expander bus has a parity bit covering all data and control signals for each clock cycle.
Parity is generated at the expander bus interface by the sender, and checked at the expander
bus interface in the receiver. Detected parity errors are reported at the receiving component
— outbound packets report parity errors in the PXB, while inbound packets report parity
errors in the MIOC.
Intel® 450NX PCIset
9-3