450NX Datasheet, PDF (127/248 Pages) Intel Corporation – Intel 450NX PCIset

12.1 Signal Specifications
Table 12-4: Signal Groups RCG
Pin Group
Signals
Notes
AGTL+ Input
BANK[2:0]#, CARD#, CMND[1:0]#, CSTB#, MA[13:0]#,
MRESET#, ROW#
AGTL+ Output
AVWP#, LDSTB#, LRD#, PHIT#, RCMPLT#, RHIT#,
WDME#
AGTL+ I/O
GRCMPLT#
CMOS Input 3.3 V
BANKID#, DR50H#, DR50T#
CMOS Input 2.5 V (3.3 V Tolerant) HCLKIN, TMS, TDI, TCK, TRST#
CMOS 14mA, 2.5 V Open Drain
Output (3.3 V Tolerant)
TDO
CMOS Output 10mA, 3.3 V
ADDR(A,B,C,D)[13:0]#, WE(A,B,C,D)(a,b)#,
CAS(A,B,C,D)(a,b,c,d)[1:0]#,
RAS(A,B,C,D)(a,b,c,d)[1:0]#
Analog Signals
CRES[1:0], VCCA, VREF[1:0]
12.1.3 The Power Good Signal: PWRGD
PWRGD is a 3.3 V-tolerant input to the PCI Bridge and memory controller components. It is
expected that this signal will be a clean indication that the clocks and the 3.3 V, VCC_PCI
supplies are within their specifications. ‘Clean’ implies that PWRGD will remain low, (capable
of sinking leakage current) without glitches, from the time that the power supplies are turned
on until they become valid. The signal will then have a single low to high transition to a high
(3. V) state with a minimum of 100ns slew rate. Figure 12-1 illustrates the relationship of
PWRGD to HCLKIN and system reset signals.
Intel® 450NX PCIset
12-3