450NX Datasheet, PDF (29/248 Pages) Intel Corporation – Intel 450NX PCIset

2.7 Common Support Signals
XpRSTB#
XpRSTFB#
PXB Reset, 2nd Version.
AGTL+ MIOC→ ext
This is a duplicate of the XpRST# signal, to be used in maintaining PLL
synchronization in the MIOC. See XpRSTFB# below.
PXB Reset, Feedback.
AGTL+ ext→ MIOC
The XpRSTB# signal is length-matched to the XpRST#’s path to the PXB,
then returned to the MIOC as the XpRSTFB# input.
2.7 Common Support Signals
2.7.1
JTAG Interface
All four components in the Intel^® 450NX PCIset have a JTAG Test Access Port (TAP) to allow
access to internal registers and perform boundary scan. Each interface is identical.
TCK
Test Clock
2.5V I
Test Clock is used to clock state information and data into and out of the
device during boundary scan.
TDI
Test Data Input
2.5V I
Test Input is used to serially shift data and instructions into the TAP.
TDO
Test Output
Test Output is used to shift data out of the device.
2.5V OD
TMS
Test Mode Select
Test Mode Select is used to control the state of the TAP controller.
2.5V I
TRST#
Test Reset
Test Reset is used to reset the TAP controller logic.
2.5V I
2.7.2
Reference Signals
All four components have the following support signals to provide voltage references or
compensation for the AGTL+ interfaces or the PLL circuitry.
CRES[1:0]
I/O Buffer Compensation Resistor Terminals
Analog I
For correct component operation an external 768 ohm resistor must be
connected between CRES1 and CRES0. This resistor should have a
minimum precision of 1%.
VCCA (n)
PLL Analog Voltage
Analog I
This pin is an independent power supply for a PLL. In normal operation, this
pin provides power to the PLL, and requires special decoupling (refer to
Electrical Characteristics).
Intel® 450NX PCIset
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