450NX Datasheet, PDF (56/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3:2 Count Mode
Selects when the counter is updated for the detected event.
0 Stop counting.
1 Count each cycle selected event occurs.
2 Count on each rising edge of the selected event.
3 Trigger. Start counting on the first rising edge of the selected
event, and continue counting each clock cycle.
1:0 Reload Mode
Reload has priority over increment. If a reload event and a count event happen
simultaneously, the count event has no effect.
0 Never Reload
1 Reload when this counter overflows.
2 Reload when the other counter overflows.
3 Reload unless the other counter increments.
3.3.34 RC: Reset Control Register
Address Offset: 42h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
The RC initiates processor reset cycles and initiates Built-in Self Test (BIST) for the
processors.
Bits Description
7:6 reserved (0)
5
Reset Expander Port #1.
While this bit is set, the X1RST# signal is asserted. When this bit is cleared, the
X1RST# pin will be deasserted, unless other assertion criteria are still in effect (e.g.,
system hard reset).
Default=0.
4
Reset Expander Port #0.
While this bit is set, the X0RST# signal is asserted. When this bit is cleared, the
X0RST# will be deasserted, unless other assertion criteria are still in effect (e.g.,
system hard reset). Default=0.
3
Processor BIST Enable (BISTE).
This bit modifies the action of the RCPU and SHRE bits, below. If this bit is set, a
subsequent invocation of system hard reset causes the INIT# signal to be asserted
coincident with the deassertion of RESET#; this combination will invoke the Built-In
Self Test (BIST) feature of the processors. Default=0.
2
Reset Processor (RCPU).
The transition of this bit from 0 to 1 causes the MIOC to initiate a hard or soft reset.
Selection of hard or soft reset, and processor BIST, are controlled by the BISTE and
SHRE enables, which must be set up prior to the 0-to-1 transition on the RCPU bit.
Default=0.
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Intel® 450NX PCIset