450NX Datasheet, PDF (73/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
13
Received Master Abort (RMA).
This bit is set when the PXB, as bus master, terminates its transaction (except for
Special Cycles) with a master abort. This bit remains set until explicitly cleared by
software writing a 1 to this bit.
Default=0.
12
Received Target Abort (RTA).
This bit is set when the PXB, as bus master, receives a target abort for its transaction.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
11
Signaled Target Abort (STA).
This bit is set when the PXB, as bus target, terminates a transaction with target abort.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
10:9 DEVSEL# Timing (DEVT).
This 2-bit field encodes the timing of the DEVSEL# signal when the PXB responds as a
target, and represents the slowest time that the PXB asserts DEVSEL# for any bus
command except Configuration Reads or Writes. This field is hardwired to the value
01b (medium).
8
Data Parity Error (DPE).
This bit is set when all of the following conditions are met:
1. The PXB asserted PERR# or sampled PERR# asserted.
2. The PXB was the initiator for the operation in which the error occurred.
3. The PERRE bit in the PCICMD register is set.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
7
Fast Back-to-Back (FB2B).
The PXB supports fast back-to-back transactions, and this bit is hardwired to 1.
6
UDF Supported.
The PXB does not support User Definable Features (UDF), and this bit is hardwired to
0.
5
66 MHz Capable.
The PXB is not capable of running at 66 MHz, and this bit is hardwired to 0.
4:0 reserved (0)
3.4.23 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DCh, E0-E4h
Default Value: 000000000000h each
Size:
40 bits each
Attribute: Read/Write
Two performance monitoring counters, with associated event selection and control registers,
are provided for each PCI bus in the PXB. The PMD registers hold the performance
monitoring count values. Event selection is controlled by the PME registers, and the action
performed on event detection is controlled by the PMR registers.
Intel® 450NX PCIset
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