450NX Datasheet, PDF (70/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3.4.16 MAR[6:0]: Memory Attribute Region Registers
Address Offset: 61-67h
Default Value: 03h for MAR[0]
00h for all others
Size:
8 bits each
Attribute: Read/Write
The Intel 450NX PCIset allows programmable memory attributes on 14 memory segments of
various sizes in the 640 Kbyte to 1 MByte address range. Seven Memory Attribute Region
(MAR) registers are used to support these features. These registers apply to both host-initiated
transactions and PCI-initiated transactions, and are therefore duplicated in both the MIOC
and PXB Configuration Spaces. Software must ensure that both sets are programmed
identically to achieve correct functioning. See the MIOC Configuration Space for a detailed
description.
3.4.17 MLT: Master Latency Timer Register
Address Offset: 0Dh
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
MLT is an 8-bit register that controls the amount of time (measured in PCI clocks) the Intel
450NX PCIset, as a bus master, can burst data on the PCI Bus. The Count Value is an 8 bit
quantity; however, MLT[2:0] are reserved and assumed to be 0 when determining the Count
Value. The number of clocks programmed in the MLT represents the guaranteed time slice
allotted to the Intel 450NX PCIset, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed.
Bits Description
7:3 Master Latency Timer Count Value.
Counter value in 8 PCI clock units.
2:0 reserved (0)
3.4.18 MMBASE: Memory-Mapped PCI Base
Address Offset: 70-71h
Default Value: 0002h
Size:
16 bits
Attribute: Read/Write
The MMBASE register specifies the starting address of this memory-mapped PCI range, and is
identical to the MMBASE register in the MIOC. The MMT register specifies the highest
address that will be directed to PCI Bus #1B, and corresponds identically to the MMR[3]
register in the MIOC. The MMBASE register must be programmed identically to the MMBASE
register in the MIOC to achieve correct functioning. See the MIOC Configuration Space for a
detailed description.
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Intel® 450NX PCIset