450NX Datasheet, PDF (75/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
5:0 Event Selection.
This field specifies the basic PCI bus transaction or PCI bus signal to be monitored.
Individual Bus Transactions
00 0000 reserved
00 0001 reserved
00 0010 I/O Read
00 0011 I/O Write
00 0100 reserved
00 0101 reserved
00 0110 Memory Read
00 0111 Memory Write
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
reserved
reserved
reserved
reserved
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write & Invalidate
Generic (Grouped) Bus Transactions
010 000 Any bus transaction
010 001 Any memory transaction
010 010 Any memory read
010 011 Any memory write
Bus Signal Assertions
011 000 reserved
011 001 reserved
011 010 RETRY¹
011 011 reserved
010 100
010 101
010 110
010 111
Any I/O transaction
Any I/O or memory transactions
Any I/O read or memory read
Any I/O read or memory write
011 100
011 101
011 110
011 111
reserved
reserved
LOCK
ACK64
All other encodings are reserved.
Note:
1. Counting data cycles is undefined for this selection.
3.4.25 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h
Default Value: 0000h each
Size:
8 bits each
Attribute: Read/Write
There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register
specifies how the event selected by the corresponding PME register affects the associated
PMD register, P(A,B)MON# pins, and the INT(A,B)RQ# pins.
Bits Description
7:6 Interrupt Assertion
Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted,
a flag for this counter is set in the Error Status Register, so that software can determine
the cause of the interrupt. This flag is reset by writing the Error Status Register.
0 Selected event does not assert INTRQ #
1 reserved
2 Assert INTRQ# pin when event occurs
3 Assert INTRQ# pin when counter overflows
5:4 Performance Monitoring pin assertion
Defines how the selected event affects the PMON# pin for this counter.
0 PMON# pin is tristated. Selected event has no effect.
1 reserved
Intel® 450NX PCIset
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