450NX Datasheet, PDF (101/248 Pages) Intel Corporation – Intel 450NX PCIset

7.1 Host To/From Memory Transactions
7.1.7
System Management Mode Accesses
The Intel 450NX PCIset uses an SMRAM configuration register to enable, define and control
access to the SMM RAM space. The SMM RAM space defaults to location A000h, with a size
of 64 KB, but may be relocated and grown in increments of 64 KB. A master enable (SMRAME)
and three access-control enables (Open, Closed, Locked) determine how accesses to the space
are to be serviced. Table 7-2 summarizes how accesses to the SMM RAM space are serviced.
Table 7-2: SMRAM Space Cycles
Code
Fetch
Data
Reference
Usage
0 X X X X Normal¹ Normal¹ SMM RAM space is not supported.
1 0 0 X 0 PCI 0a
1 0 0 X 1 DRAM
PCI 0a
DRAM
Normal SMM usage. Accesses to the SMM
RAM space from processors in SMM will
access the DRAM. Accesses by processors
not in SMM will be diverted to the
compatibility PCI bus.
1 0 1 X 0 PCI 0a
1 0 1 X 1 DRAM
PCI 0a
PCI 0a
A modification of the normal SMM usage, in
which only code fetches are accepted from
processors in SMM mode.
1 1 X 0 X DRAM
DRAM
Full access by any agent to SMM RAM
space. Typically used by the BIOS to
initialize SMM RAM space.
1. SMRAM functions are disabled. The access is serviced like any other. The address is checked
against the other space and gap definitions to determine its disposition -- to PCI, to memory, or to
the system bus for a third party agent to claim.
7.1.8
Third-Party Intervention
The Intel 450NX PCIset supports the same third-party control sideband controls that were
defined in Intel 450GX PCIset. These controls allow an external agent on the system bus to
affect the way in which the MIOC responds to a system bus request to memory. This external
agent is referred to as a “third-party” to the transaction. When a third-party agent intervenes
in the normal transaction flow, both the MIOC and the third-party share responsibility for
generating the appropriate response; however, the MIOC is always the “owner” of the
transaction, and hence must be the responding bus agent.
The third-party controls how the MIOC responds by asserting a code on the sideband
TPCTL[1:0] signals during the snoop phase. The MIOC samples these signals in the last cycle
of the snoop phase. Table 7-3 indicates the actions possible using the TPCTL[1:0] signals.
Intel® 450NX PCIset
7-3