450NX Datasheet, PDF (137/248 Pages) Intel Corporation – Intel 450NX PCIset

12.4 AC Specifications
Table 12-12: Intel^® 450NX PCIset MIOC AC Specifications (Continued)
Vcc₃ = 3. 3V (5%, T_CASE = 0 to 85 ^oC)
Symbol Parameter
Setup
Min
Hold
Min
Expander Interface
(two per
MIOC:0,1)
T21
X(0,1)RST#,
X(0,1)RSTB#
T23
X(0,1)RSTFB#,
1.88
0.63
X(0,1)XRTS#
T11
X(0,1)HRTS#
Other
T39
CRESET#
T25
ERR[1:0]#
2.0
0.5
T70
INTREQ#, SMI-
ACT#
T71
PWRGD
4.0
1.0
T70
PWRGDB
T21
RESET#
Testability
Signals:
T26
TRST#
T27
TMS
5.0
14.0
T27
TDI
5.0
14.0
T28
TDO
T29
TDO on/off delay
Delay
Min
Delay
Max
Unit Notes
-0.1
3.25
-0.15
2.65
1.0
4.1
1.0
5.0
0.0
3.5
0.0
3.5
-0.1
3.25
ns
7, 8
ns
ns
8
ns
3
ns
10
ns
3
ns
1, 6
ns
3, 5, 13
ns
7, 8, 12
ns
4, 6
ns
2
ns
2
1.0
10.0
ns
2, 3
25.0
ns
2, 3
Notes:
1. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD
signal.
2. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
3. Min and Max timings are measured with 0pF load.
4. TRST# requires a pulse width of 40 ns.
5. This output is asynchronous.
6. This input is asynchronous.
7. Asynchronous assertion with synchronous deassertion.
8. Min and Max timings are measured with 0pf and 25 Ohms to Vtt.
9. Min and Max timings are measured with 0pf and 150 Ohms to 2.5 V.
10. Min and Max timings are measured with 0pf and 230 Ohm to 3.3 V.
11. See Table 12-16 for source synchronous timings.
12. Minimum pulse width 1.0ms.
13. PWRGDB is the buffered output of PWRGD, and has no relation to HCLKIN.
Intel® 450NX PCIset
12-13