450NX Datasheet, PDF (95/248 Pages) Intel Corporation – Intel 450NX PCIset

6.1 Overview
bus. There are two MUX components per board to provide a 72-bit data path from each of
four possible interleaved quad-words to the MD bus. This is illustrated in Figure 6-3.
Memory
Card
MUX
MUX
MD[71:0]
DSTBP[3:0]#,
DSTBN[3:0]#
To MIOC
Figure 6-3: Memory Card Datapath
To other memory card
6.1.2
Configuration Rules and Limitations
Memory array configurations are governed by the following rules:
• Either one or two cards can be populated in a working system.
• Any number of memory rows, on either card, can be populated in a working system.
• Memory banks can be populated in any order on either card.
• Cards designed to support 4:1 interleaving will also support 2:1 interleaves (in the first
bank only).
• Within any given row, the populated interleaves must have DIMMs of uniform size.
• Memory sizes (16 MB vs. 64 MB) may be mixed within a memory card, but must be the
same within a bank.
• Memory speeds (60ns or faster) may be mixed, but all four banks within an RCG operate
at the same speed, and must therefore be configured to the slowest DIMM in the set.
6.1.2.1
Interleaving
The Intel 450NX PCIset supports 4:1 interleaving across all banks, and 2:1 interleaving in the
first bank of card #0 only. The Intel 450NX PCIset does not support non-interleaved
configurations. Interleave configuration register programming must be consistent across the
entire memory system. For example, if one bank is configured as 4:1 then the entire memory
sub-system must be 4:1 and the associated memory bank configuration registers must be
programmed as 4:1.
To support a 4:1 interleave requires two MUXs. Supporting a 2:1 interleave requires only one
MUX. A two-MUX design will also support 2:1 interleaves. An entry-level card (i.e., 2:1
Intel® 450NX PCIset
6-3