450NX Datasheet, PDF (41/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3.7
CVDR: Configuration Values Driven On Reset
Address Offset: 4C-4Dh
Default Value: 0000h
Size:
16 bits
Attribute: Read/Write, Sticky
During RESET# assertion, and for one host clock past the trailing edge of RESET#, the MIOC
drives the contents of this register onto the A[15:0]# pins.
Bits Description
15:13 reserved (0)
12:11
APIC Cluster ID.
This two-bit field representing the APIC Cluster identifier is driven to A#[12:11]
during RESET#. Note that there are no pins to input the cluster ID; software must
explicitly load the value into this register. Default=0.
10
reserved (0)
9
Enable BERR# Input.
If set, A#[9] will be asserted during RESET#, and all system bus agents will enable
BERR# observation. Default=0.
8
Enable AERR# Input.
If set, A#[8] will be asserted during RESET#, and all system bus agents will enable
AERR# observation. Default=0.
7
In-Order Queue Depth 1.
If set, A#[7] will be asserted during RESET#, and all Pentium^® II Xeon™ processors
on the system bus will limit their In-Order Queue Depth to 1 (no pipelining support),
instead of their usual 8. Default=0.
6
1M Power-on Reset Vector.
If set, A#[6] will be asserted during RESET#, and all Pentium II Xeon processors on
the system bus will use the 1MB-1 (000FFFFFh) reset vector, instead of their usual
4 GB-1 (FFFFFFFFh) vector. Default=0.
5
Enable FRC Mode.
If set, A#[5] will be asserted during RESET#, and all Pentium II Xeon processors on
the system bus will enter FRC enabled mode. Default=0.
4:0 reserved (0)
3.3.8
DBC[15:0]: DRAM Bank Configuration Registers
Address Offset: 80-9Fh
Default Value: A200h each
Size:
16 bits each
Attribute: Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one RCG and four
banks per card) for a maximum of 8 GB of memory. This corresponds to DBC[0:3] on the first
card and DBC[8:11] on the second card.
Intel® 450NX PCIset
3-9