450NX Datasheet, PDF (114/248 Pages) Intel Corporation – Intel 450NX PCIset

10. System Initialization
5. All system bus devices will capture the system configuration parameters from the
appropriate system bus lines on the rising edge of RESET#. The MIOC captures these
values in its Configuration Values Captured on Reset (CVCR) register. (This allows an
external device to over-ride the MIOC default parameters.)
6. All system bus devices are now ready for further programming. The MIOC will respond
to BIOS code fetches.
7. If a change in the system bus system configuration is desired, the MIOC’s CVDR register
can be programmed with the desired values.
8. After the CVDR register is programmed, the MIOC must be programmed to do a hard
reset, through the Reset Control (RC) register.
9. When the MIOC performs a hard reset, all system bus devices are again reset. This reset
repeats steps 2-8, except that the CVDR register is not effected by the reset. This register is
only re-initialized by the PWRGD signal.
10.1.1.2 Special Considerations for Third-Party Agents
One of the settings available in the CVDR/CVCR registers allows the Bus In-Order Queue
Depth to be set to 1, instead of the usual 8. When IOQ Depth=1, there is a case where a Third-
Party Agent can starve the system bus.
Therefore, any system containing a TPA must either:
• require that the TPA back-off its BPRI# arbitration requests sufficiently to allow the
symmetric agents access to the bus, or
• not use IOQ depth=1.
10-2
Intel® 450NX PCIset