450NX Datasheet, PDF (110/248 Pages) Intel Corporation – Intel 450NX PCIset

9. Data Integrity & Error Handling
MEL and MEA registers. For bus errors, the error type, syndrome and chunk are logged. The
first two system bus errors (single-bit or multi-bit) will be logged in the HEL registers.
All ECC error logging registers are sticky through reset, allowing software to determine the
source of an error after restoring the system to functioning mode. The logging registers hold
their values until explicitly cleared by software.
Error Signaling Mechanism
Single-bit correctable errors are not critical from the point-of-view of presenting the correct
value of data to the system. The DRAM (if the cause of error is a DRAM array) will still
contain faulty data which will cause the repetition of error detection and recovery for the
subsequent accesses to the same location.
Multi-bit uncorrectable errors are fatal system errors and will cause the MIOC to assert the
BERR# signal if enabled in the ERRCMD register. The uncorrected data is forwarded to its
destination. For the first two multi-bit uncorrectable errors, the MIOC will log in the MEA
register the row number where the error occurred. This information can be used later to point
to a faulty DRAM DIMM.
The MEA/MEL registers log only the first two errors. After the first two errors have been
logged, the MEA/MEL registers will not be updated. However, normal error detection still
continues, the ERR[1:0]# and BERR# signals are still asserted as appropriate, and scrubbing
of the memory still continues.
9.1.4
Memory Scrubbing
The Intel 450NX PCIset provides a “scrub-on-error” (demand scrubbing) mechanism, wherein
corrected data for single-bit errors will be automatically written back into the memory
subsystem by the MIOC. Note that this is not the same as “walk-through” scrubbing, in
which every memory location is systematically accessed, checked and corrected on a regular
basis. The scrub-on-error mechanism will scrub only those locations accessed during normal
operation and thus complements the software controlled “walk-through” scrubbing.
9.1.5
Debug/Diagnostic Support
The MIOC supports in-system testing of ECC functions. An ECC Mask Register (ECCMSK)
can be programmed with a masking function. Subsequent writes into memory will store a
masked version of the computed ECC. Subsequent reads of the memory locations written
while masked will return an invalid ECC code. If the mask register is left at 0h (the default),
the normal computed ECC is written to memory.
9.2
System Bus Integrity
A variety of system bus error detection features are provided by the MIOC. Particularly, the
system data bus is checked for ECC errors on Host-DRAM and Host-PCI writes.
9-2
Intel® 450NX PCIset