450NX Datasheet, PDF (5/248 Pages) Intel Corporation – Intel 450NX PCIset

CONTENTS
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
3.4.19
3.4.20
3.4.21
3.4.22
3.4.23
3.4.24
3.4.25
3.4.26
3.4.27
3.4.28
3.4.29
3.4.30
3.4.31
3.4.32
3.4.33
GAPEN: Gap Enables ................................................................................................................
HDR: Header Type Register ......................................................................................................
HXGB: High Expansion Gap Base .............................................................................................
HXGT: High Expansion Gap Top ...............................................................................................
IOABASE: I/O APIC Base Address ............................................................................................
ISA: ISA Space ..........................................................................................................................
LXGB: Low Expansion Gap Base ..............................................................................................
LXGT: Low Expansion Gap Top ................................................................................................
MAR[6:0]: Memory Attribute Region Registers ..........................................................................
MLT: Master Latency Timer Register .........................................................................................
MMBASE: Memory-Mapped PCI Base .....................................................................................
MMT: Memory-Mapped PCI Top ...............................................................................................
MTT: Multi-Transaction Timer Register .....................................................................................
PCICMD: PCI Command Register .............................................................................................
PCISTS: PCI Status Register ....................................................................................................
PMD[1:0]: Performance Monitoring Data Register .....................................................................
PME[1:0]: Performance Monitoring Event Selection ..................................................................
PMR[1:0]: Performance Monitoring Response ..........................................................................
RID: Revision Identification Register .........................................................................................
RC: Reset Control Register .......................................................................................................
ROUTE: Route Field Seed .........................................................................................................
SMRAM: SMM RAM Control Register .......................................................................................
TCAP: Target Capacity ..............................................................................................................
TMODE: Timer Mode .................................................................................................................
TOM: Top of Memory .................................................................................................................
VID: Vendor Identification Register ............................................................................................
3-36
3-36
3-36
3-36
3-37
3-37
3-37
3-37
3-38
3-38
3-38
3-39
3-39
3-39
3-40
3-41
3-42
3-43
3-44
3-44
3-45
3-45
3-46
3-46
3-47
3-47
Chapter 4
System Address Maps ....................................................................................................................... 4-1
4.1 Memory Address Map ................................................................................................................................. 4-1
4.1.1 Memory-Mapped I/O Spaces ........................................................................................................ 4-4
4.1.2 SMM RAM Support ....................................................................................................................... 4-4
4.2 I/O Space .................................................................................................................................................... 4-5
4.3 PCI Configuration Space ............................................................................................................................. 4-6
Chapter 5
Interfaces ............................................................................................................................................. 5-1
5.1 System Bus ................................................................................................................................................. 5-1
5.2 PCI Bus ....................................................................................................................................................... 5-1
5.3 Expander Bus .............................................................................................................................................. 5-1
5.3.1 Expander Electrical Signal and Clock Distribution ........................................................................ 5-2
5.4 Third-Party Agents ...................................................................................................................................... 5-2
5.5 Connectors .................................................................................................................................................. 5-3
Chapter 6
Memory Subsystem ............................................................................................................................ 6-1
6.1 Overview ..................................................................................................................................................... 6-1
6.1.1 Physical Organization ................................................................................................................... 6-1
6.1.2 Configuration Rules and Limitations ............................................................................................. 6-3
6.1.2.1 Interleaving .................................................................................................................. 6-3
6.1.2.2 Address Bit Permuting Rules and Limitations ............................................................. 6-4
6.1.2.3 Card to Card (C2C) Interleaving Rules and limitations ................................................ 6-4
6.1.3 Address Bit Permuting .................................................................................................................. 6-5
Intel® 450NX PCIset
-iii-