450NX Datasheet, PDF (19/248 Pages) Intel Corporation – Intel 450NX PCIset

2.3 System Interface
D[63:0]#
DBSY#
DEP[7:0]#
DEFER#
DRDY#
HIT#
HITM#
INIT#
LOCK#
REQ[4:0]#
RP#
RS[2:0]#
Data
AGTL+ I/O
These signals are connected to the system data bus. The data signals are
inverted on the system bus.
Data Bus Busy
AGTL+ I/O
Used by the data bus owner to hold the data bus for transfers requiring more
than one cycle.
Data Bus ECC/Parity
AGTL+ I/O
These signals provide parity or ECC for the D#[63:0] signals. The MIOC only
provides ECC.
Defer
AGTL+ I/O
DEFER# is driven by the addressed agent to indicate that the transaction
cannot be guaranteed to be globally observed.
Data Ready
Asserted for each cycle that valid data is transferred.
AGTL+ I/O
Hit
AGTL+ I
The MIOC never asserts HIT#; it has no cache, and never snoop stalls.
Hit Modified
AGTL+ I
The MIOC never asserts HITM#; it has no cache, and never snoop stalls.
Soft Reset
2.5V OD
INIT# may be asserted to request a soft reset of the processors. During a
system hard reset, the INIT# signal may be optionally asserted to cause the
processors to initiate their BIST. The INIT# signal is not asserted during
power-good reset.
Lock
AGTL+ I
All system bus cycles sampled with the assertion of LOCK# and ADS#, until
the negation of LOCK#, must be atomic; i.e., no PCI activity to DRAM is
allowed and the locked cycle must be translated to PCI if targeted for the PCI
bus.
Request Command
AGTL+ I/O
Asserted during both clocks of a request phase. In the first clock, the signals
define the transaction type to a level which is sufficient to begin a snoop
request. In the second clock, the signals carry additional information to define
the complete transaction type.
Request Parity
AGTL+ I/O
Even parity protection on ADS# and REQ[4:0]#. It is valid on both cycles of
the request.
Response Signals
Indicate response type as shown below:
000 Idle state
001 Retry
010 Deferred
011 reserved
100 Hard failure
101 No Data
110 Implicit writeback
111 Normal Data
AGTL+ I/O
Intel® 450NX PCIset
2-7