450NX Datasheet, PDF (76/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
2 Assert this counter’s PMON# pin when event occurs
3 Assert this counter’s PMON# pin when counter overflows
3:2 Count Mode
Selects when the counter is updated for the detected event.
0 Stop counting.
1 Count each cycle selected event is active.
2 Count on each rising edge of the selected event.
3 Trigger. Start counting on the first rising edge of the selected event, and
continue counting each clock cycle.
1:0 Reload Mode
Reload has priority over increment. That is, if a reload event and a count event
happen simultaneously, the count event has no effect.
0 Never reload
1 Reload when this counter overflows.
2 Reload when the other counter overflows.
3 Reload unless the other counter increments.
3.4.26 RID: Revision Identification Register
Address Offset: 08h
Default Value: 00h
Bits Description
Size:
8 bits
Attribute: Read Only
7:0 Revision Identification Number.
This is an 8-bit value that indicates the revision identification number for the PXB.
These bits are read only and writes to this register have no effect.
3.4.27 RC: Reset Control Register
Address Offset: 47h
Default Value: 01h
Size:
8 bits
Attribute: Read/Write/Sticky
The RC register controls the response of the PXB to XRST#.
Bits Description
7:1 reserved (0)
0
Reset PCI clocks on XRST#
Clearing this bit enables PCICLKA and PCICLKB to run undisturbed through reset.
When set, PCI clock phase will be reset whenever XRST# is asserted.
When clear, System Hard Resets, PXB Resets, Soft Resets, BINIT Resets will not
disturb PCICLKA and PCICLKB. This bit is defined to be sticky so that it can only be
modified by PWRGD or configuration write. Default=1.
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Intel® 450NX PCIset