450NX Datasheet, PDF (52/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3.3.27 MEA[1:0] Memory Error Effective Address
Address Offset: A8-A9h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write, Sticky
These registers contain the effective address information needed to identify the specific
DIMM that produced the error.
Bits Description
7
Card.
Holds the card number (0,1) where the suspect DIMM resides.
6:4 Bank.
Identifies the bank within the card (0..7) where the suspect DIMM resides.
3
Row.
Identifies the row within the bank (for double row DIMMs).
2
reserved (0)
1:0 Effective Address [4:3].
These two bits of the effective address indicate the "starting" Qword in the critical
order access. When combined with the chunk number of the error, as logged in the
MEL registers, this identifies the specific DIMM where the error occurred.
3.3.28 MEL[1:0] Memory Error Log
Address Offset: B0-B3h
Default Value: 0000h each
Size:
16 bits each
Attribute: Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data retrieved from
the memory. MEL[0] logs the first error, and MEL[1] logs the second.
Bits Description
15:8 Syndrome.
Holds the calculated syndrome that identifies the specific bit in error.
7:4 reserved (0)
3:2 Chunk Number.
Specifies which of the four possible chunks in the critical chunk ordered transfer the
error occurred in, from zero to three.
1
Multiple-Bit Error Logged (MBE).
This flag is set if the logged error was a multiple-bit (uncorrectable) error.
0
Single-Bit Error Logged (SBE).
This flag is set if the logged error was a single-bit (correctable) error.
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Intel® 450NX PCIset