450NX Datasheet, PDF (12/248 Pages) Intel Corporation – Intel 450NX PCIset

1. Introduction
System Management Features
• Provides controlled access to the Intel Architecture System Management Mode (SMM)
memory space (SM RAM).
Test & Tuning Features
• Signal interconnectivity testing via boundary scan.
• Access to internal control and status registers via JTAG TAP port.
I2C access is not provided in the PCIset; however, error indicators are reported to pins
which can be monitored and sampled using I2C capabilities if provided elsewhere in the
system.
• System bus, memory and I/O performance counters with programmable events.
Reliability/Availability/Serviceability (RAS) Features
• ECC coverage of system data bus and memory; parity coverage of system bus controls,
PCI bus, and Expander bus.
• ECC bits can be corrupted via selective masking for diagnostics.
• Fault recording of the first two ECC errors. Each includes error type and syndrome.
Memory ECC error logs include the effective address, allowing identification of the failing
location. Error logs are not affected by reset, allowing recovery software to examine the
logs.
1.4
Packaging & Power
• Table 1-1 indicates the signal count, package and power for each component in the Intel^®
450NX PCIset. In a common high-end configuration, using two memory cards (each with
one RCG and two MUX components), two PXBs and 3.3 V supplies, the Intel 450NX
PCIset would contribute approximately 47 watts.
Table 1-1: Signals, Pins, Packaging and Power
Chip
MIOC
PXB
Signals
348
177
Package
PLGA-540²
PLGA-540²
RCG
173 BGA-324
MUX
207 BGA-324
Notes:
1. Assumes 3.3 V supplies.
2. Requires heat sink.
Footprint
42.5 mm
42.5 mm
27.0 mm
27.0 mm
Power¹
13.2 W
7.8 W
2.5 W
3.3 W
1-4
Intel® 450NX PCIset