450NX Datasheet, PDF (106/248 Pages) Intel Corporation – Intel 450NX PCIset

8. Arbitration, Buffers & Concurrency
8.2.1
Third Party Arbitration
The Intel 450NX PCIset requests the system bus with BPRI#. If multiple bridges or a third
party agent is on the system bus, an arbitration method is required to establish bus ownership
among multiple requesting bridges (which bridge can drive BPRI#). This arbitration is
transparent to the Pentium^® II Xeon™ processors or other symmetric bus agents. Only one
bridge is allowed to drive BPRI# at a time.
8.3
South Bridge Support
The Intel^® 450NX PCIset is designed to work with the PIIX4E south bridge which connects the
PCI bus to ISA bus and I/O APIC components. Note that the protocols described here apply
only when the Intel 450NX PCIset is used in internal arbiter mode — use of the PIIX4E in
external arbiter configurations is not supported.
The Intel 450NX PCIset does not guarantee ISA access latencies of < 2.5 usec. ISA devices
which require these latencies to be met (GAT mode timing) are not supported.
8.3.1
I/O Bridge Configuration Example.
The basic I/O bridge configuration supported by the Intel 450NX PCIset is shown in Figure 8-
1. The figure shows the sideband signals that connect the PXB to the PIIX4E, I/O APIC
components and the external arbiter. Note that PHOLD#/PHLDA# are connected between
PXB and the PIIX4E, and WSC# output from PXB is connected to the APICACK2# input of the
stand-alone I/O APIC component. If the configuration does not have I/O APIC component,
then WSC# pin is left unconnected.
REQ#[0:5]
GNT#[0:5]
PHLDA#
EXTARB
NC
PHOLD#
PXB
WSC#
PCI bus
PHOLD#
PHLDA#
APICREQ#
APICACK#
PIIX4E
APICREQ#
APICACK# APICACK2#
I/O APIC
Figure 8-1: ISA Bridge with the I/O APIC (Internal Arbiter)
8-2
Intel® 450NX PCIset