450NX Datasheet, PDF (113/248 Pages) Intel Corporation – Intel 450NX PCIset

System Initialization ₁₀
10.1 Post Reset Initialization
10.1.1 Reset Configuration Using CVDR/CVCR
All system bus devices must sample the following configuration options at reset:
• Address/request/response parity checking: Enabled or Disabled
• AERR# detection enable
• BERR# detection enable
• BINIT# detection enable
• FRC mode: Enabled or Disabled
• Power-on reset vector: 1M or 4G
• In-Order Queue depth: 1 or 8
• APIC cluster ID: 0, 1, 2, or 3
• Symmetric agent arbitration ID: 0, 1, 2, 3
The MIOC provides both the Symmetric Arbitration ID parameter and other parameters.
(Refer to the CVDR register description.)
10.1.1.1
Configuration Protocol
A Pentium^® II Xeon™ processor-based system is initialized and configured in the following
manner.
1. The system is powered. The power-supply provides resets for the Intel^® 450NX PCIset
through the PWRGD signal. The MIOC and PXBs assert their resets while the PWRGD
signal is not asserted. PCI reset is driven to tristate the PCI buses in order to prevent PCI
output buffers from short circuiting when the PCI power rails are not within the specified
tolerances.
2. All Intel 450NX PCIset components are initialized, with their internal registers defaulting
to the power-on values.
3. The MIOC will drive the appropriate system bus data lines with the initial configuration
values that defaulted in the Configuration Values Driven on Reset (CVDR) register.
4. On the rising edge of RESET#, the MIOC will continue driving the appropriate system
bus lines with the configuration values. These values are driven at least one clock after the
rising edge of RESET#.
Intel® 450NX PCIset
10-1