450NX Datasheet, PDF (50/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3.3.23 ISA: ISA Space
Address Offset: 7Ch
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register defines the ISA Space address range. If enabled, memory-mapped accesses into
this address range will be forwarded to the compatibility PCI bus. This space is defined to
support ISA cards incapable of using the full 32-bit PCI address.
Bits Description
7:6 reserved (0)
5:4 ISA Space Size.
This field specifies the size of the gap. Legal sizes are:
00b: 1 MB 10b: 4 MB
01b: 2 MB 11b: 8 MB
3:0 ISA Space Base Address.
This 4-bit field specifies the A[23:20] portion of the gap’s base address. The A[43:24]
and A[19:0] portions of the gap’s base address are zero.
3.3.24 LXGB: Low Expansion Gap Base
Address Offset: 54-55h
Default Value: 0000h
Bits Description
Size:
16 bits
Attribute: Read/Write
15:12 reserved (0)
11:0 Gap Base Address.
This field specifies the A[31:20] portion of the gap’s base address, in 1 MB increments.
The A[43:32] and A[19:0] portions of the gap’s base address are zero.
3.3.25 LXGT: Low Expansion Gap Top
Address Offset: 56-57h
Default Value: 0000h
Bits Description
Size:
16 bits
Attribute: Read/Write
15:12 reserved (0)
11:0 Gap Top Address.
This field specifies the A[31:20] portion of the gap’s highest address, in 1 MB
increments. The A[43:32] portion of the gap’s top address is zero, while the A[19:0]
portion of the gap’s top address is FFFFFh.
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Intel® 450NX PCIset