450NX Datasheet, PDF (79/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
This register allows nominally fixed-duration timers to be adjusted to shorter values for test
purposes.
Bits Description
7:2 reserved (0)
1:0 Delayed Read Request Expiration Counter.
This counter is strictly for test purposes. Changing it from the default value is a
violation of the PCI specification.
00 normal mode (2¹⁵ clocks)
01 128 clocks
10 64 clocks
11 16 clocks
3.4.32 TOM: Top of Memory
Address Offset: 50-52h
Default Value: 000FFFh
Size:
24 bits
Attribute: Read/Write
This register specifies the highest physical address that could be directed to the memory. This
register applies to both host-initiated transactions and PCI-initiated inbound transactions, and
is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must
ensure that both sets are programmed identically to achieve correct functioning. See the
MIOC Configuration Space for a detailed description.
3.4.33 VID: Vendor Identification Register
Address Offset: 00 - 01h
Default Value: 8086h
Size:
16 bits
Attributes: Read Only
Bits Description
15:0 Vendor Identification Number.
This is a 16-bit value assigned to Intel. Intel VID = 8086h.
Intel® 450NX PCIset
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