450NX Datasheet, PDF (43/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3.10 DID: Device Identification Register
Address Offset: 02 - 03h
Default Value: 84CAh
Bits Description
Size:
16 bits
Attributes: Read Only
15:0 Device Identification Number.
The value 84CAh indicates the Intel^® 450NX PCIset MIOC.
3.3.11 ECCCMD: ECC Command Register
Address Offset: B8h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register controls the Intel 450NX PCIset responses to ECC errors on data retrieved from
the memory subsystem or received from the system bus.
Bits Description
7
reserved (0)
6
System Bus, Report Multi-Bit Errors (HRM).
If set, the Intel^® 450NX PCIset will log multiple-bit ECC errors on data received from
the system bus in the appropriate HEL register. If the BERR# driver is enabled,
BERR# will also be asserted. Default=0.
5
System Bus, Report Single-Bit Errors (HRS).
If set, on detection of a single-bit ECC error on data received from the system bus the
Intel 450NX PCIset will log the error in the appropriate HEL register, and assert the
INTREQ# signal. Default=0.
4
System Bus, Correct Single-Bit Errors (HCS).
If set, on detection of a single-bit ECC error on data received from the system bus the
Intel 450NX PCIset will correct the data and generate a new ECC code before writing
the data into memory. Default=0.
3
Memory, Scrub Single-Bit Errors (MSS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will perform a scrub operation to correct the location in the
memory. The MCS bit in this register must be set for this feature to be effective.
Default=0.
2
Memory, Report Multi-Bit Errors (MRM).
If set, on detection of a multiple-bit ECC error on data read from the memory array
the Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers. If
the BERR# driver is enabled, BERR# will also be asserted. Default=0.
Intel® 450NX PCIset
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