450NX Datasheet, PDF (42/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
Unused DBC registers should be configured as inactive, with the Bank Present bit cleared and
the TOB field set to that of the previous bank, indicating that the amount of memory in that
bank is zero.
Bits Description
15
4:1 Interleave.
If set, bank is a 4:1 interleave. If cleared, bank is a 2:1 interleave.
Default=1.
14
Single Row.
This bit is set if the bank contains only a single row. If cleared, the bank contains two
rows; both rows must be configured identically. Default=0.
13
Bank Present.
This bit is set to indicate that this memory bank is present, and refresh cycles should
be issued to the bank. This bit must be cleared if this bank is not physically present.
Default=1.
12:10 reserved (0)
9:0 Top of Bank (TOB).
This field contains the effective address of the top of memory in this bank and all lower
banks, and is used to determine which bank is selected. Each TOB field specifies the
amount of memory, in 32 MB chunks, contained in this bank and all lower banks.
Unpopulated banks must have their TOB set equal to that of the previous bank
indicating that the amount of memory in that bank is zero.
Default = 200h, each.
3.3.9
DEVMAP: System Bus PCI Device Map
Address Offset: D6-D7h
Default Value: 0005h
Size:
16 bits
Attribute: Read/Write, Read Only
This register indicates which PCI devices on the system bus have active configuration spaces.
At reset, DEVMAP is initialized with all devices not present except the MIOC and the
compatibility PCI bus.
Bits Description
15
reserved (0)
14:0 PCI Bus #0, Device [30:16] Present.
Each bit corresponds to a device on PCI Bus #0 (numbers 16-30). If set, the device is
present in the system and is expected to respond to configuration cycles directed to it.
Bit 0 is hardwired "on", and is read-only.
Default=0005h (MIOC, PCI #0A present)
3-10
Intel® 450NX PCIset