450NX Datasheet, PDF (55/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
00 0110 reserved
00 0111 reserved
Generic (Grouped) Bus Transactions
010 000 Any bus transaction
010 001 Any memory transaction
010 010 Any memory read
010 011 Any memory write
Bus Signal Assertions
011 000 HIT^1,2
011 001 HITM^1,2
011 010 RETRY^1,2
011 011 DEFER^1,2
Memory Hits/Misses
100 000 Bank was idle^1,2
100 001 Waited for Row precharge^1,2
00 1110 Memory Read
00 1111 Memory Write
010 100
010 101
010 110
010 111
Any I/O transaction
Any I/O or memory transactions
Any I/O or memory read
Any I/O or memory write
011 100
011 101
011 110
011 111
BNR^1,2
BPRI²
LOCK²
reserved
100 010 Waited for address lines^1,2
100 011 Hit open page^1,2
All other encodings are reserved.
Notes:
1. Counting data cycles is undefined for this selection.
2. The Agent, Destination and Length fields cannot be applied to this selection,
and should be programmed to "any".
3.3.33 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
The PMR register specifies how the event selected by the corresponding PME register affects
the associated PMD register, the BP[1:0] pins, and the INTREQ# pin. Events defined by
PME[0] can be driven out BP0 and events defined by PME[1] can be driven out BP1.
Bits Description
7:6 Interrupt Assertion
Defines how selected event affects INTREQ# assertion. Whenever INTREQ# is
asserted, a flag for this counter is set in the Error Status (ERRSTS) register, so that
software can determine the cause of the interrupt. This flag is reset by writing the
ERRSTS register.
0 Selected event does not assert INTREQ#
1 reserved
2 Assert INTREQ# pin when event occurs
3 Assert INTREQ# pin when counter overflows
5:4 Performance Monitoring pin assertion
Defines how the selected event affects the Performance Monitoring pin for this
counter.
0 Selected event does not assert this counters PM pin
1 reserved
2 Assert this counter’s PM pin when event occurs
3 Assert this counter’s PM pin when counter overflows
Intel® 450NX PCIset
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