450NX Datasheet, PDF (93/248 Pages) Intel Corporation – Intel 450NX PCIset

Memory Subsystem ₆
6.1
Overview
The Intel 450NX^® PCIset’s memory subsystem consists of one or two memory cards. Each
card is comprised of one RCG component, a DRAM array, and two MUX components. Table
6-1 summarizes the Intel 450NX PCIset’s general memory characteristics.
Table 6-1: General Memory Characteristics
DRAM type
Memory modules
DRAM technologies
Interleaves
Memory size
Extended Data Out (EDO)
72-bit, single and double high DIMMs
16 Mbit and 64 Mbit
50 and 60 nsec
3.3 V
4:1, 2:1 (in bank 0, of card 0)
2:1 interleave: 32 MB
4:1 interleave: 64 MB to 8 GB, in 64 MB increments
6.1.1
Physical Organization
The Intel^® 450NX PCIset supports up to 8 banks of memory, configured across one or two
memory cards. Each bank can support up to 1 GB using 64 Mbit double-high DIMMs to
provide a total of 8 GB of memory in 8 banks. Each bank can support one or two rows of 2 or 4
interleaves. Each row represents a set of memory devices simultaneously selected by a RAS#
signal. Each interleave generates 72 bits (64 data, 8 ECC) of data per row using one DIMM.
Four interleaves provide a total of 256 bits of data (32 bytes) which is one cache line for the
Pentium^® II Xeon™ processor. Data from multiple interleaves are combined by the MUXs to
exchange 72 bits of data with the MIOC at an effective rate of one cache line every 30ns
(effective rate: 1.067 GB/s) for a 4-way interleaved memory. Figure 6-1 illustrates this
configuration.
The RCG and MUX Components
The RCGs generate the signals to control accesses to the main memory DRAMs. The RCG
initiates no activity until it receives a command from the MIOC. The maximum number of
RCGs per Intel 450NX PCIset system is two. Each RCG controls up to four banks of DRAM.
Each bank of memory may consist of one (for single-sided DIMMs) or two (for double-sided
or double-high DIMMs) rows. Internally, each RCG component contains four RAS/CAS
control units (RCCUs), each dedicated to one bank of DRAM. This is illustrated in Figure 6-2.
Each MUX component has four 36-bit data I/O connections to DRAM (one 18-bit path for
each of four possible interleaved quad-words) and one 36-bit data I/O connection to the MD
Intel® 450NX PCIset
6-1