450NX Datasheet, PDF (60/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
3.3.41 SUBB[1:0]: Bus B Subordinate Bus Number, per PXB
Address Offset: D2h, D5h
Default Value: 00h each
See the description of BUSNO.
Size:
8 bits each
Attribute: Read/Write
3.3.42 TCAP[0:3]: Target Capacity, per PXB/PCI Port
Address Offset: C0-C2h, C4-C6h
C8-CAh, CC-CEh
Default Value: 041082 each
Size:
24 bits each
Attribute: Read/Write
Each of these registers is programmed by software with the maximum number of transactions
and data bytes that the receiving PXB/PCI port can accept for outbound transactions.
Register Controls outbound transactions to ... if in ...
dual 32-bit Bus Mode 64-bit Bus Mode
TCAP[0] PXB #0 / PCI Bus A
PXB #0
TCAP[1] PXB #0 / PCI Bus B
N/A
TCAP[2] PXB #1 / PCI Bus A
PXB #0
TCAP[3] PXB #1/ PCI Bus B
N/A
NOTE
Setting a value below the listed minimum-allowed value will have unpredictable results, up to and
including potential deadlocks requiring a hard reset of the PCIset.
Bits Description
23:18
Outbound Write Transaction Capacity.
This field specifies the total number of outbound write transactions, per PXB/PCI
port, that can be forwarded and queued by the PXB.
MIOC maximum: 12
Minimum allowed: 1, 2 or 3 Default= 1
- If no outbound locks are supported, then the minimum is 1.
- If ordinary outbound locks are supported, then the minimum is 2.
- If outbound split locks are supported, then the minimum is 3.
17:12
Outbound Read Transaction Capacity.
This field specifies the total number of outbound read transactions, per PXB/PCI port,
that can be forwarded and queued in the PXB.
MIOC maximum: 2
Minimum allowed: 1
Default= 1
11:6 Outbound Write Data Buffer Capacity.
This field specifies the total number of data buffers, per PXB/PCI port, available in
the PXB for use by outbound write transactions, in increments of 32 bytes.
MIOC maximum: 12
Minimum allowed: 2
Default= 2
3-28
Intel® 450NX PCIset