450NX Datasheet, PDF (143/248 Pages) Intel Corporation – Intel 450NX PCIset

12.4 AC Specifications
DSTBx#
XHSTBx#
XXSTBx#
MD(71:0)#
XD(15:0)#
XBE[1:0]#
XPAR#
T80
T81
T81
XADS#
XBLK#
Figure 12-8: Source Synchronous Signal to Strobe Timings (at source)
Table 12-18: 100 MHz Source Synchronous Timing (at destination)
Symbol Parameter
Setup
Min
Hold
Min
Unit Notes
T20
DSTBN(3:0)#,
7.0
DSTBP(3:0)#
X(0,1)XSTBN#
X(0,1)XSTBP#
T24
MD(71:0)#
1.5
1.5
T22
X(0,1)D[15:0]#, 1.75
1.0
X(0,1)ADS#,
X(0,1)BE[1:0]#,
X(0,1)BLK#,
X(0,1)D[15:0]#,
X(0,1)PAR#
ns
1,4
ns
2
ns
3
Notes:
1.
2.
3.
4.
Setup in relation to “capture” HCLKIN.
With respect to the DSTBs.
With respect to the HSTBs.
Applies to Expander bus source synchronous signals. For synchronous signals (RTS#) the maximum
clock skew between MIOC and PXB plus the flight time must not exceed 4.97nS.
Intel® 450NX PCIset
12-19