450NX Datasheet, PDF (86/248 Pages) Intel Corporation – Intel 450NX PCIset

4. System Address Maps
Restricted-Access Addresses
By default, all Host-PCI I/O writes will be posted. However, in traditional Intel-architecture
systems, there are certain I/O addresses to which posting is not desirable, due to ordering
side effects. Table 4-1 lists the I/O addresses for which I/O write posting will not be
supported, regardless of the posting enable in the MIOC’s CONFIG register. These accesses
will be deferred instead.
Address
0020h-0021h
0060h-0064h
0070h
0092h
00A0h-00A1h
00F0h
0CF8h, 0CFCh
Table 4-1: Non-Postable I/O Addresses
Function
8259A Interrupt Controller, Master, Interrupt Masks
Keyboard controller: com/status and data
NMI# Mask
A20 Gate
8259A Interrupt Controller, Slave, Interrupt Masks
IGNNE#, IRQ13
PCI configuration space access
4.3
PCI Configuration Space
The Intel^® 450NX PCIset provides a PCI-compatible configuration space for the MIOC, and
two in the PXB—one for each PCI bus. I/O reads and writes issued on the system bus are
normally claimed by the MIOC and forwarded through the PXBs as I/O reads and writes on
the PCI bus. However, I/O accesses to the 0CF8h and 0CFCh addresses are defined as special
configuration accesses for I/O devices.
Each configuration space is selected using a Bus Number and a Device Number within that
bus. PCI buses are numbered in ascending order within hierarchical buses. PCI Bus #0
represents both the compatibility PCI bus as well as the devices in the Intel 450NX PCIset and
any third party agents attached to the system bus.
The MIOC and each PCI bus within each PXB in the system is assigned a unique Device
Number on Bus #0, as shown in Table 4-2. The PXBs are numbered based on the Expander
bus port used.
Table 4-2: Device Numbers for Bus Number 0 ^{1 2}
Device
Number
10h
11h
12h
13h
Device
MIOC
reserved
PXB 0, Bus a ³
PXB 0, Bus b
Device
Number
18h
19h
1Ah
1Bh
Device
4-6
Intel® 450NX PCIset