450NX Datasheet, PDF (28/248 Pages) Intel Corporation – Intel 450NX PCIset

2. Signal Descriptions
XpD[15:0]#
XpHRTS#
XpHSTBP#
XpHSTBN#
XpPAR#
XpXRTS#
XpXSTBP#
XpXSTBN#
Datapath
AGTL+ MIOC↔ PXB
This bidirectional datapath is used to transfer addresses and data between the
MIOC and the PCI Expander.
Host Request to Send.
AGTL+ MIOC→ PXB
Request to use the bidirectional Expander bus sent from MIOC to PXB,
synchronous to HCLKIN.
Host Strobes
AGTL+ MIOC→ PXB
This pair of opposite-phase strobes are used by the PXB to latch and
synchronize incoming data.
Bus Parity.
AGTL+ MIOC↔ PXB
Bidirectional signal indicating even parity across XD[15:0] and XBE[1:0].
Expander Request to Send.
AGTL+ PXB→ MIOC
Request to use the bidirectional Expander bus sent from PXB to MIOC,
synchronous to HCLKIN.
Expander Strobes
AGTL+ PXB→ MIOC
This pair of opposite-phase strobes are used by the MIOC to latch and
synchronize incoming data.
Support Signals
XpBLK
Block Counters.
AGTL+ MIOC→ PXB
This signal is asserted when the Performance Counter Master Enable bit in
the MIOC’s CONFIG register is set, and is used to affect a nearly
simultaneous stop/start of the performance counters across both the MIOC
and all PXBs.
XpCLK
Host Clock.
CMOS MIOC→ PXB
This is the primary clock source provided to the PXB, analogous to HCLKIN
for the MIOC, RCG and MUX. Inside the PXB, it is divided by 3 to produce a
PCI clock output at 33.33 MHz from an HCLKIN of 100 MHz.
XpCLKB
Host Clock, 2nd Version.
CMOS MIOC→ ext
This is a duplicate of the XpCLK signal, to be used in maintaining PLL
synchronization in the MIOC. See XpCLKFB below.
XpCLKFB
Host Clock, Feedback.
CMOS ext→ MIOC
This signal is a length-matched copy of the XpCLK signal sent to the PXB,
used to maintain PLL synchronization in the MIOC. The XpCLKB signal is
length-matched to the XpCLK’s path to the PXB, then returned to the MIOC
as the XpCLKFB input.
XpIB
Driving Inbound.
AGTL+ PXB→ ext
This active-high signal is asserted when the PXB is driving data over the
Expander bus. This pin is not connected to the MIOC.
XpRST#
PXB Reset.
AGTL+ MIOC→ PXB
This signal issues a hard reset of the PXB, including the dependent PCI buses.
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Intel® 450NX PCIset