450NX Datasheet, PDF (117/248 Pages) Intel Corporation – Intel 450NX PCIset

11.2 System Reset
82C42
A20M#, INTR,
NMI#, IGNE#
frequency
select
logic
Power
Good
Processor
Processor
...
A20M#,IGNE#,
INTR,NMI#
CRESET#
PWRGD
MIOC
RESET#
BINIT#
MRESET#
PWRGDB
System
Bus
RCG Mux
Memory
Card #0
RCG Mux
Memory
Card #1
PIIXOK#
PXB #1
PXB #0
PIIXOK#
CPURST
PWRGD
Figure 11-3: Recommended RESET Distribution for Intel^® 450NX
PCIset-Based Systems Including a PIIX4E South Bridge
Power Good
The reference system shown here assumes a single "power good" signal that indicates clean
power supplies and clocks to the MIOC and both PXBs. For routing convenience and drive
capability, the MIOC provides a buffered version of its PWRGD input (PWRGDB), which
should be connected to the PWRGD inputs of each PXB. Refer to the Electrical Characteristics
for additional PWRGD requirements.
RESET#
The RESET# signal is directed to the processors. Assertion of this signal puts all processors in
a known state, and invalidates their L1 and L2 caches. When this signal is deasserted, the
processor begins to execute from address 00_FFFF_FFF0h. The Boot ROM must respond to
this address range regardless of where it physically resides in the system.
CRESET#
The CRESET# signal tracks RESET#, but is held asserted two clocks longer than RESET#. It
is provided to allow an external frequency selection mux to drive the system-bus-to-core-clock
ratio onto pins LINT[1:0], IGNNE#, and A20M# of the system bus during RESET#.
Intel® 450NX PCIset
11-3