450NX Datasheet, PDF (49/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3.21 IOAR: I/O APIC Ranges
Address Offset: 6A-6Bh
Default Value: 0000h
Size:
16 bits
Attribute: Read/Write
Each of the three fields in the IOAR register specifies the highest APIC number (0-15) that
should be directed to that PCI bus, for buses 0A, 0B and 1A. All higher APIC ID are directed
to PCI Bus 1B.
Bits Description
15:12 reserved (0)
11:8 PCI Bus #1A Highest APIC ID (BUS1A).
This field represents the highest APIC ID that should be directed to PCI Bus #1A.
7:4 PCI Bus #0B Highest APIC ID (BUS0B).
This field represents the highest APIC ID that should be directed to PCI Bus #0B.
3:0 PCI Bus #0A Highest APIC ID (BUS0A).
This field represents the highest APIC ID that should be directed to PCI Bus #0A.
3.3.22 IOR: I/O Ranges
Address Offset: 7E-7Fh
Default Value: 0FFFh
Size:
16 bits
Attribute: Read/Write
The IOR register defines the I/O range addresses for each PCI bus. These are specified in
sixteen 4 KB segments. The starting (base) address for PCI Bus #0A is 0h.
Bits Description
15:12 reserved (0)
11:8 PCI Bus #1A Upper Address (BUS1A).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #1A. The A[11:0] portion of this address is FFFh.
7:4 PCI Bus #0B Upper Address (BUS0B).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #0B. The A[11:0] portion of this address is FFFh.
3:0 PCI Bus #0A Upper Address (BUS0A).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #0A. The A[11:0] portion of this address is FFFh.
If PXB x is operating in 64-bit bus mode, BUSxB must equal BUSxA.
Intel® 450NX PCIset
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