450NX Datasheet, PDF (90/248 Pages) Intel Corporation – Intel 450NX PCIset

5. Interfaces
Byte enable information for data fields. All 18 of these bits are protected by an even parity
signal. Two synchronous arbitration signals (one in each direction) are used for each
Expander bus.
5.3.1
Expander Electrical Signal and Clock Distribution
The Expander bus is designed to allow multiple high bandwidth I/O ports to be added to the
Intel^® 450NX PCIset with minimal impact on signal pin count. The Expander bus also
provides flexibility in server system topology by allowing the I/O subsystem to be located
away from the main PCIset. This flexibility is achieved with a signaling scheme that uses a
combination of synchronous and source synchronous clocking. This is illustrated in Figure 5-
1.
MIOC
Strobe
Synch
HCLKIN
PXB
RST
R _PLL
FB
R _PLL
FB
Core CLK
Expander Bus
HRTS#
XRTS#
XADS#
XBE[1:0]
XD[15:0]
XPAR
HSTBP#
HSTBN#
XSTBP#
XSTBN#
XRSTFB#
XRSTB#
(L1)
XRST#
(L2)
XCLK
(L3)
XCLKB
XCLKFB
(L4)
PXB
Strobe
Synch
Required length matching: L1=L2=L3=L4
Figure 5-1: Expander Bus Clock Distribution
5.4
Third-Party Agents
In addition to the processors and the Intel^® 450NX PCIset, the Pentium^® II Xeon™ processor
bus allows for additional bus masters, generically referred to as third-party agents (TPA).
These agents may be symmetric agents, in which case they must participate in the bus
arbitration algorithm used by the processors. They may also be priority agents, in which case
they must negotiate with the Intel 450NX PCIset for control of the system bus.
5-2
Intel® 450NX PCIset