450NX Datasheet, PDF (44/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
1
Memory, Report Single-Bit Errors (MRS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers, and
assert the INTREQ# signal. Default=0.
0
Memory, Correct Single-Bit Errors (MCS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will correct the data and generate a new ECC code before
returning the data to the requestor. Default=0.
3.3.12 ECCMSK: ECC Mask Register
Address Offset: B9h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register is used to test the ECC error detection logic in the memory subsystem. The
register is written with a masking function which is applied on subsequent writes to memory.
All subsequent writes into memory will store a masked version of the computed ECC.
Subsequent reads of the memory locations written while masked will return an invalid ECC
code. To disable testing, the mask value is left at 0h (default).
Bits Description
7:0 ECC Generation Mask.
Each bit of the computed ECC is XOR’ed with the corresponding bit in this mask field
before it is stored in the memory array.
3.3.13 ERRCMD: Error Command Register
Address Offset: 46h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register controls the MIOC responses to various system and data errors.
Bits Description
7:6 reserved (0)
5
BERR#-to-BINIT# Enable.
If set, on observation or assertion of BERR#, (and Enable BERR# Input is set) the MIOC
will also assert BINIT#.
Default=0.
4
Fast System Bus Time-out.
This bit controls the duration of a watchdog timer which is started at the end of the
system bus response phase. If this bit is set, the timer expires in 256 host cycles. If
cleared, the timer expires in 2¹⁷ cycles.
Default=0.
3-12
Intel® 450NX PCIset