450NX Datasheet, PDF (65/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
8
Outbound Write Around Retried/Partial Read Enable.
If set, the PXB allows outbound writes to pass retried or partially completed (i.e.,
disconnected) outbound reads. This enable must be set for Pentium^® II Xeon™
processor/Intel^® 450NX PCIset systems. Default=1.
7
Burst Write Combining Enable (BWCE).
If set, back-to-back sequentially addressed outbound writes may be combined in the
outbound write buffers before placement on the PCI bus. When the BWCE is cleared,
all outbound write combining is disabled, and each host transaction results in a
corresponding transaction on the PCI bus. Default=0.
6
Re-streaming Buffer Enable.
If set, the data returned and buffered for a Delayed Inbound Read may be re-accessed
following a disconnect. If cleared, following a disconnect, the buffer is invalidated,
and a subsequent read to the next location will initiate a new read. Default=0
(Disabled).
5:4 Read Prefetch Size.
This field configures the number of Dwords that will be prefetched on Memory Read
Multiple commands. Legal values are:
00 16 Dwords (2 x 32 bytes) 10 64 Dwords (8 x 32 bytes)
01 32 Dwords (4 x 32 bytes) 11 reserved
The normal selection is 32 Dwords The 64 Dword selection provides highest
performance when the PXB is in 64-bit bus mode. Default=01 (32 Dwords).
3
External Arbiter Enable.
This is a read-only bit that selects internal or external arbitration for the PCI bus. The
bit reflects the state of the P(A,B)XARB# strapping pin for this bus (A or B).
Default=[P(A,B)XARB pin].
2
64-bit Bus Enable.
This is a read-only bit that selects whether the PXB operates as two 32-bit PCI buses or
a single 64-bit PCI bus. The bit reflects the state of the MODE64# strapping pin.
Default=[MODE64# pin].
1
Host/PCI Bus Gearing Ratio.
This is a read-only bit that selects the system clock to PCI clock gearing ratio. The bit
reflects the state of the GEAR4# strapping pin. This bit should be cleared (i.e.,
GEAR4# is high, or deasserted), resulting in a system clock/ PCI clock gearing ratio
of 3:1.
Default=[GEAR4# pin].
0
reserved
3.4.5
DID: Device Identification Register
Address Offset: 02 - 03h
Default Value: 84CBh
Size:
16 bits
Attributes: Read Only
Intel® 450NX PCIset
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