450NX Datasheet, PDF (26/248 Pages) Intel Corporation – Intel 450NX PCIset

2. Signal Descriptions
DSEL#
Data Card Select
AGTL+ MIOC→ MUX
This signal, when qualified by the DVALID# signal, selects which card the
memory transfer is coming from or destined towards. Each memory card uses
a single DSEL# input, sent to each MUX on the card. The MIOC provides two
DSEL# outputs (DSEL[1:0]#), one sent to each card.
DVALIDa#
DVALIDb#
Data Transfer Complete
AGTL+ MIOC→ MUX
This signal indicates that the DSEL[1:0]#, DOFF[1:0]#, and WDEVT# signals
are valid. Typically the “a” signal connects the MIOC and all MUXs on Card
#0, while the “b” signal connects the MIOC and all MUXs on Card #1.
GDCMPLT#
Global DCMPLT#
AGTL+, I/O, all MUXs
A “global” version of the DCMPLT(a,b)# signals, asserted coincident with
DCMPLT#, and by the same agent. Whereas each DCMPLT# signal connects
the MUXs on one card with the MIOC, the GDCMPLT# signal connects the
MUXs across both cards while excluding the MIOC. This allows all MUXs to
monitor each data completion without placing undue loading on the
DCMPLT# signals.
WDEVT#
Write Data Event
AGTL+ MIOC→ MUX
This signal, when qualified by the DVALID# signal, indicates the type of data
transfer command. If asserted, the command represents a write data transfer.
If deasserted, the command represents a read data transfer.
2.5.2 Internal Interface
2.5.2.1
RCG / DRAM Interface
Each RCG provides four sets of signals to drive four banks in the DRAM array. In each of the
following signal names, the "ß" indicates a set of signals per bank. Each RCG controls four
banks; therefore ß = A, B, C or D.
CASß(a,b,c,d)[1:0]#
Column Address Strobes
LVTTL RCG→ DRAM
These signals are used to latch the column address into the DRAMs. The “a”,
“b”, “c” and “d” versions are duplicates for load reduction.
ADDRß[13:0] DRAM Address
LVTTL RCG→ DRAM
ADDR is used to provide the multiplexed row and column address to DRAM.
RASß(a,b,c,d)[1:0]#
Row Address Strobe
LVTTL RCG→ DRAM
The RAS signals are used to latch the row address into the DRAMs. Each
signal is used to select one DRAM row. The 1:0 signals indicate which row
within the bank. The “a”, “b”, “c” and “d” versions are duplicates for load
reduction.
WEß(a,b)#
Write Enable Signal
LVTTL RCG→ DRAM
WE# is asserted during writes to main memory. The “a” and “b” versions are
duplicates for load reduction.
2-14
Intel® 450NX PCIset