450NX Datasheet, PDF (10/248 Pages) Intel Corporation – Intel 450NX PCIset

1. Introduction
Bus. Each PXB provides two independent 32-bit, 33 MHz PCI buses, with an option to link the
two buses into a single 64-bit, 33 MHz bus. The Intel 450NX PCIset memory subsystem
supports one or two memory cards. Each card is comprised of an RCG, a DRAM array, and
two MUXs. The MIOC issues requests to the RCG components on each card to generate RAS#,
CAS#, and WE# outputs to the DRAMs. The MUX components provide the datapath for the
DRAM arrays. Up to 8 GB of memory in various configurations are supported.
Other capabilities of the Intel 450NX PCIset include:
• Full Pentium^® II Xeon™ processor bus interface (36-bit address, 64-bit data) at 100 MHz.
• Support for two dedicated PCI expander bridges (PXBs) attached behind the system bus so
as not to add additional electrical load to the system bus.
• Support for both internal and external system bus and I/O bus arbitration.
Supporting Devices
The Intel 450NX PCIset is designed to support the PIIX4E south bridge. The PIIX4E is a highly
integrated mulit-functional component that supports the following capabilities:
• PCI Rev 2.1-compliant PCI-to-ISA Bridge with support for 33-MHz PCI operations
• Enhanced DMA controller
• 8259 Compatible Programmable Interrupt Controller
• System Timer functions
• Integrated IDE controller with Ultra DMA/33 support
1.2
Intel^® 450NX PCIset Components
MIOC Memory and I/O Bridge Controller
The MIOC accepts access requests from the system bus and directs those accesses to
memory or one of the PCI buses. The MIOC also accepts inbound requests from the
PCI buses. The MIOC provides the data port and buffering for data transferred
between the system bus, PXBs and memory. In addition, the MIOC generates the
appropriate controls to the RCG and MUX components to control data transfer to and
from the memory.
PXB PCI Expander Bridge
The PXB provides the interface to two independent 32-bit, 33 MHz Rev 2.1-compliant
PCI buses. The PXB is both a master and target on each PCI bus.
RCG
RAS/CAS Generator
The RCG is responsible for accepting memory requests from the MIOC and
converting these into the specific signals and timings required by the DRAM. Each
RCG controls up to four banks of memory.
MUX
Data Path Multiplexor
The MUX provides the multiplexing and staging required to support memory
interleaving between the DRAMs and the MIOC. Each MUX provides the data path
for one-half of a Qword for each of four interleaves.
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Intel® 450NX PCIset